1. Technical Field
The present invention relates to solid-state imaging devices and manufacturing methods thereof.
2. Related Art
Heretofore, CCD sensors have been mainly used in solid-state imaging devices. However, development of CMOS sensors that can be driven at a low voltage and on which a peripheral circuit can be incorporated has been progressing rapidly. Countermeasures against noise that include process measures such as complete transfer technology and a dark current prevention structure and circuit measures such as CDS have been applied to the CMOS sensors, and as a result the image quality thereof has become comparative to that of the CCD sensors. Now the CMOS sensors exceed the CCD sensors in quality and in production volume. The rapid advancement of the CMOS sensors is attributed to a large improvement in image quality, and the improvement in image quality was realized by an improvement in charge transfer techniques and the like. Technologies for improving charge transfer techniques are disclosed in Japanese Patents No. 3,403,061 and No. 3,600,430.
FIG. 12A is a cross-sectional view illustrating a known solid-state imaging device, and FIG. 12B is a potential diagram when charges are transferred from X to Y shown in FIG. 12A in the case where a transfer gate is on and off.
The solid-state imaging device shown in FIG. 12A includes an N-type silicon substrate 101 and a P-well (P−) 102 formed in the N-type silicon substrate 101. A gate insulating film 106 is formed on the P-well 102, and a transfer gate electrode 107 is formed on the gate insulating film 106. A pinning layer (P+) 104 is formed in the P-well 102 so as to be outside the transfer gate electrode 107 and start from a first end portion 107a thereof in plan view. A diffusion layer of an N−-type impurity region 103 is formed in the P-well 102 so as to extend under the pinning layer 104. A diffusion layer of an N+-type impurity region (floating diffusion) 105 is formed in the P-well 102 in a portion that includes a portion that is under a second end portion 107b of the transfer gate electrode 107.
In the known solid-state imaging device described above, a structure has been adopted in which the N−-type impurity region 103 that includes a portion under the first end portion 107a of the transfer gate electrode 107 and constitutes a photodiode extends under the transfer gate electrode 107. This structure is the main factor for avoiding the formation of a transfer barrier. However, in this structure, when the extension amount of the N−-type impurity region 103 under the transfer gate electrode 107 becomes too large, a problem arises in that a potential well (dip) is formed. In this case, a problem arises in that, when a charge transfer 108 is performed, charges are trapped in the potential well, and a charge transfer failure occurs (refer to FIG. 12B).
On the other hand, in the case where the extension amount of an N−-type impurity region 103a under the transfer gate electrode 107 is small, as shown in FIG. 13A, a problem arises in that a charge transfer failure occurs due to a potential barrier (refer to FIG. 13B). FIG. 13A is a cross-sectional view illustrating another known solid-state imaging device, and FIG. 13B is a potential diagram when charges are transferred from X to Y shown in FIG. 13A in the case where a transfer gate is on and off. The solid-state imaging device shown in FIG. 13A differs from the solid-state imaging device shown in FIG. 12A in that the extension amount of the N−-type impurity region 103a under the transfer gate electrode 107 is almost zero, and other configurations are the same.
As described above, it has been difficult to control the extension amount of the N−-type impurity region 103 or 103a under the transfer gate electrode 107 such that the potential well (refer to FIG. 12B) and the potential barrier (refer to FIG. 13B) are not formed. Specifically, it has been difficult to realize a structure, with high controllability, with which the potential well and the potential barrier are prevented from forming when the charge transfer is performed at a low voltage.